H8SXSLASH1663 datasheet(873/1158 Pages) RENESAS

873 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 821 of 1102

REJ09B0294-0100

17.3.1

2C Bus Control Register A (ICCRA)

ICCRA enables or disables I

2C bus interface, controls transmission or reception, and selects

master or slave mode, transmission or reception, and transfer clock frequency in master mode.

Bit

Bit Name

Initial Value

R/W

ICE

R/W

RCVD

R/W

MST

R/W

TRS

R/W

CKS3

R/W

CKS2

R/W

CKS1

R/W

CKS0

R/W

Bit

Bit Name

Initial

Value

R/W

Description

ICE

R/W

2C Bus Interface Enable

0: This module is halted

1: This bit is enabled for transfer operations (SCL and

SDA pins are bus drive state)

RCVD

R/W

Reception Disable

This bit enables or disables the next operation when

TRS is 0 and ICDRR is read.

0: Enables next reception

1: Disables next reception

MST

TRS

R/W

Master/Slave Select

Transmit/Receive Select

When arbitration is lost in master mode, MST and

TRS are both reset by hardware, causing a transition

to slave receive mode. Modification of the TRS bit

should be made between transfer frames.

Operating modes are described below according to

MST and TRS combination.

00: Slave receive mode

01: Slave transmit mode

10: Master receive mode

11: Master transmit mode

CKS3

CKS2

CKS1

CKS0

R/W

Transfer Clock Select 3 to 0

These bits are valid only in master mode. Make

setting according to the required transfer rate. For

details on the transfer rate, see table 17.2.

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