H8SXSLASH1663 datasheet(875/1158 Pages) RENESAS

875 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 823 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

BBSY

R/W

Bus Busy

This bit indicates whether the I

2C bus is occupied or

released and to issue start and stop conditions in

master mode. This bit is set to 1 when the SDA level

changes from high to low under the condition of SCL =

high, assuming that the start condition has been

issued. This bit is cleared to 0 when the SDA level

changes from low to high under the condition of SDA =

high, assuming that the stop condition has been

issued. Follow this procedure also when re-transmitting

a start condition. To issue a start or stop condition, use

the MOV instruction.

SCP

R/W

Start/Stop Condition Issue

This bit controls the issuance of start or stop condition

in master mode.

To issue a start condition, write 1 to BBSY and 0 to

SCP. A re-transmit start condition is issued in the same

way. To issue a stop condition, write 0 to BBSY and 0

to SCP. This bit is always read as 1. If 1 is written, the

data is not stored.

SDAO

This bit monitors the output level of SDA.

0: When reading, the SDA pin outputs a low level

1: When reading the SDA pin outputs a high level



R/W

Reserved

The write value should always be 1.

SCLO

This bit monitors the SCL output level.

When reading and SCLO is 1, the SCL pin outputs a

high level. When reading and SCLO is 0, the SCL pin

outputs a low level.



Reserved

This bit is always read as 0.

IICRST

R/W

IIC Control Module Reset

This bit reset the IIC control module except the I

registers. If hang-up occurs because of communication

failure during I

2C operation, by setting this bit to 1, the



Reserved

This bit is always read as 1.

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