H8SXSLASH1663 datasheet(872/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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872 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 820 of 1102

REJ09B0294-0100

17.3

The I

2C bus interface 2 has the following registers.

Channel 0:

• I2C bus control register A_0 (ICCRA_0)

• I2C bus control register B_0 (ICCRB_0)

• I2C bus mode register_0 (ICMR_0)

• I2C bus interrupt enable register_0 (ICIER_0)

• I2C bus status register_0 (ICSR_0)

• Slave address register_0 (SAR_0)

• I2C bus transmit data register_0 (ICDRT_0)

• I2C bus receive data register_0 (ICDRR_0)

• I2C bus shift register_0 (ICDRS_0)

Channel 1:

• I2C bus control register A_1 (ICCRA_1)

• I2C bus control register B_1 (ICCRB_1)

• I2C bus mode register_1 (ICMR_1)

• I2C bus interrupt enable register_1 (ICIER_1)

• I2C bus status register_1 (ICSR_1)

• Slave address register_1 (SAR_1)

• I2C bus transmit data register_1 (ICDRT_1)

• I2C bus receive data register_1 (ICDRR_1)

• I2C bus shift register_1 (ICDRS_1)

H8SX/1663 数据表(PDF) 872 Page - Renesas Technology Corp