H8SXSLASH1663 datasheet(878/1158 Pages) RENESAS

878 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 826 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When the TDRE bit in ICSR is set to 1, this bit enables

or disables the transmit data empty interrupt (TXI)

request.

0: Transmit data empty interrupt (TXI) request is

disabled

1: Transmit data empty interrupt (TXI) request is

enabled

TEIE

R/W

Transmit End Interrupt Enable

This bit enables or disables the transmit end interrupt

(TEI) request at the rising of the ninth clock while the

TDRE bit in ICSR is set to 1. The TEI request can be

canceled by clearing the TEND bit or the TEIE bit to 0.

0: Transmit end interrupt (TEI) request is disabled

1: Transmit end interrupt (TEI) request is enabled

RIE

R/W

Receive Interrupt Enable

This bit enables or disables the receive full interrupt

(RXI) request when receive data is transferred from

ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.

The RXI request can be canceled by clearing the

RDRF or RIE bit to 0.

0: Receive data full interrupt (RXI) request is disabled

1: Receive data full interrupt (RXI) request is enabled

NAKIE

R/W

NACK Receive Interrupt Enable

This bit enables or disables the NACK receive interrupt

(NAKI) request when the NACKF and AL bits in ICSR

are set to 1. The NAKI request can be canceled by

clearing the NACKF or AL bit, or the NAKIE bit to 0.

0: NACK receive interrupt (NAKI) request is disabled

1: NACK receive interrupt (NAKI) request is enabled

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