H8SXSLASH1663 datasheet(947/1158 Pages) RENESAS

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Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 895 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description



R/W

Programming Mode Related Setting Error Detect

Detects the error protection state and returns the result.

When the error protection state is entered, this bit is set

to 1. Whether the error protection state is entered or not

can be confirmed with the FLER bit in FCCS. For

conditions to enter the error protection state, see section

21.8.3, Error Protection.

0: Normal operation (FLER = 0)

1: Error protection state, and programming cannot be

performed (FLER = 1)



R/W

Programming Execution Error Detect

Writes 1 to this bit when the specified data could not be

written because the user MAT was not erased. If this bit

is set to 1, there is a high possibility that the user MAT

has been written to partially. In this case, after removing

the error factor, erase the user MAT.

0: Programming has ended normally

1: Programming has ended abnormally (programming

result is not guaranteed)



R/W

Flash Key Register Error Detect

Checks the FKEY value (H'5A) before programming

starts, and returns the result.

0: FKEY setting is normal (H'5A)

1: FKEY setting is abnormal (value other than H'5A)



Unused

Returns 0.



R/W

Write Data Address Detect

When an address not in the flash memory area is

specified as the start address of the storage destination

for the program data, an error occurs.

0: Setting of the start address of the storage

destination for the program data is normal

1: Setting of the start address of the storage

destination for the program data is abnormal

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