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H8SX/1663 数据表(PDF) 948 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 948 Page - Renesas Technology Corp

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Section 21 Flash Memory (0.18-
µm F-ZTAT Version)
Rev.1.00 Jun. 07, 2006 Page 896 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
1
WA
R/W
Write Address Error Detect
When the following items are specified as the start
address of the programming destination, an error
occurs.
• An area other than flash memory
• The specified address is not aligned with the 128-
byte boundary (lower eight bits of the address are
other than H'00 and H'80)
0: Setting of the start address of the programming
destination is normal
1: Setting of the start address of the programming
destination is abnormal
0
SF
R/W
Success/Fail
Returns the programming result.
0: Programming has ended normally (no error)
1: Programming has ended abnormally (error occurs)
(c)
Erasure
FPFR indicates the return value of the erasure result.
7
6
MD
5
EE
4
FK
3
EB
0
SF
2
1
Bit
Bit Name
Bit
Bit Name
Initial
Value
R/W
Description
7
Unused
Returns 0.
6
MD
R/W
Erasure Mode Related Setting Error Detect
Detects the error protection state and returns the result.
When the error protection state is entered, this bit is set
to 1. Whether the error protection state is entered or not
can be confirmed with the FLER bit in FCCS. For
conditions to enter the error protection state, see section
21.8.3, Error Protection.
0: Normal operation (FLER = 0)
1: Error protection state, and programming cannot be
performed (FLER = 1)



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