H8SXSLASH1663 datasheet(950/1158 Pages) RENESAS

950 / 1158 page

Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 898 of 1102

REJ09B0294-0100

(3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU)

FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI

ranges from 8 MHz to 50 MHz.



Bit

Bit Name



Bit

Bit Name

F15

F14

F13

F12

F11

F10

Bit

Bit Name

Bit

Bit Name

Bit

Bit Name

Initial

Value

R/W

Description

31 to 16



Unused

These bits should be cleared to 0.

15 to 0

F15 to F0



R/W

Frequency Set

These bits set the operating frequency of the CPU.

When the PLL multiplication function is used, set the

multiplied frequency. The setting value must be

calculated as follows:

1. The operating frequency shown in MHz units must

be rounded in a number of three decimal places and

be shown in a number of two decimal places.

2. The value multiplied by 100 is converted to the

binary digit and is written to FPEFEQ (general

For example, when the operating frequency of the CPU

is 35.000 MHz, the value is as follows:

1. The number of three decimal places of 35.000 is

rounded.

2. The formula of 35.00

× 100 = 3500 is converted to

the binary digit and B'0000 1101 1010 1100

(H'0DAC) is set to ER0.

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