H8SXSLASH1663 datasheet(1019/1158 Pages) RENESAS

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Section 22 Clock Pulse Generator

Rev.1.00 Jun. 07, 2006 Page 967 of 1102

REJ09B0294-0100

22.6

Usage Notes

22.6.1

Notes on Clock Pulse Generator

1. The following points should be noted since the frequency of

φ (Iφ: system clock, Pφ:

peripheral module clock, B

φ: external bus clock) supplied to each module changes according

to the setting of SCKCR.

Select a clock division ratio that is within the operation guaranteed range of clock cycle time

cyc shown in the AC timing of electrical characteristics.

The frequency should be set under the conditions of 8 MHz

≤ Iφ ≤ 50 MHz, 8 MHz ≤ Pφ ≤ 35

MHz, and 8 MHz

≤ Bφ ≤ 50 MHz.

2. All the on-chip peripheral modules (except for the DMAC and DTC) operate on the P

φ. Note

therefore that the time processing of modules such as a timer and SCI differs before and after

changing the clock division ratio.

In addition, wait time for clearing software standby mode differs by changing the clock

division ratio. For details, see section 23.7.3, Setting Oscillation Settling Time after Clearing

Software Standby Mode.

3. The relationship among the system clock, peripheral module clock, and external bus clock is I

≥ Pφ and Iφ ≥ Bφ. In addition, the system clock setting has the highest priority. Accordingly,

φ or Bφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits

PCK2 to PCK0 or BCK2 to BCK0.

4. Note that the frequency of

φ will be changed in the middle of a bus cycle when setting SCKCR

while executing the external bus cycle with the write-data-buffer function.

5. Figure 22.9 shows the clock modification timing. After a value is written to SCKCR, this LSI

waits for the current bus cycle to complete. After the current bus cycle completes, each clock

frequency will be modified within one cycle (worst case) of the external input clock

φ.

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