H8SXSLASH1663 datasheet(1034/1158 Pages) RENESAS

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Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 982 of 1102

REJ09B0294-0100

3. Clearing by

STBY pin

When the

STBY pin level is driven low, a transition is made to hardware standby mode.

4. Clearing by reset caused by watchdog timer overflow

Sleep mode is exited by an internal reset caused by a watchdog timer overflow.

23.6

All-Module-Clock-Stop Mode

When the ACSE bit is set to 1 and all modules controlled by MSTPCRA/MSTPCRB are stopped

(MSTPCRA/MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer are stopped

(MSTPCRA/MSTPCRB = H'F[C to F]FFFFFF), executing a SLEEP instruction with the SSBY

bit in SBYCR cleared to 0 will cause all modules (except for the 8-bit timer*, watchdog timer, and

32K timer), the bus controller, and the I/O ports to stop operating, and to make a transition to all-

module-clock-stop mode at the end of the bus cycle.

When further reduction in power consumption is necessary in all-module-clock-stop mode, stop

the modules controlled by MSTPCRC (MSTPCRC[15 to 8] = H'FFFF).

All-module-clock-stop mode is cleared by an external interrupt (NMI or

IRQ0 to IRQ11 pins),

RES pin, or an internal interrupt (8-bit timer*, watchdog timer, or 32K timer), and the CPU

returns to the normal program execution state via the exception handling state. All-module-clock-

stop mode is not cleared if interrupts are disabled, if interrupts other than NMI are masked on the

CPU side, or if the relevant interrupt is designated as a DTC activation source.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Note: * Operation or halting of the 8-bit timer can be selected by bits MSTPA9 and MSTPA8

in MSTPCRA.

H8SX/1663 数据表(PDF) 1034 Page - Renesas Technology Corp