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H8SX/1663 数据表(PDF) 1036 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 1036 Page - Renesas Technology Corp

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Section 23 Power-Down Modes
Rev.1.00 Jun. 07, 2006 Page 984 of 1102
REJ09B0294-0100
23.7.3
Setting Oscillation Settling Time after Clearing Software Standby Mode
Bits STS4 to STS0 in SBYCR should be set as described below.
1. Using a crystal resonator
Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time.
Table 23.2 shows the standby times for operating frequencies and settings of bits STS4 to
STS0.
2. Using an external clock
A PLL circuit settling time is necessary. Refer to table 23.2 to set the standby time.
Table 23.2
Oscillation Settling Time Settings
P
φ* [MHz]
STS4 STS3 STS2 STS1 STS0
Standby
Time
35
25
20
Unit
0
0
0
0
0
Reserved
µs
1
Reserved
1
0
Reserved
1
Reserved
1
0
0
Reserved
1
64
1.8
2.6
3.2
1
0
512
14.6
20.5
25.6
1
1024
29.3
41.0
51.2
1
0
0
0
2048
58.5
81.9
102.4
1
4096
0.12
0.16
0.20
ms
1
0
16384
0.47
0.66
0.82
1
32768
0.94
1.31
1.64
1
0
0
65536
1.87
2.62
3.28
1
131072
3.74
5.24
6.55
1
0
262144
7.49
10.49
13.11
1
524288
14.98
20.97
26.21
1
0
0
0
0
Reserved
: Recommended time setting when using an external clock.
: Recommended time setting when using a crystal resonator.
Note:
*
P
φ is the output from the peripheral module frequency divider.



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