H8SXSLASH1663 datasheet(1033/1158 Pages) RENESAS

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Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 981 of 1102

REJ09B0294-0100

23.4

Module Stop Function

Module stop function can be set for individual on-chip peripheral modules.

When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module

operation stops at the end of the bus cycle and a transition is made to the module stop state. The

CPU continues operating independently.

When the corresponding MSTP bit is cleared to 0, the module stop state is cleared and the module

starts operating at the end of the bus cycle. In the module stop state, the internal states of modules

other than the SCI are retained.

After the reset state is cleared, all modules other than the DMAC, DTC, and on-chip RAM are in

the module stop state.

The registers of the module for which the module stop state is selected cannot be read from or

written to.

23.5

Sleep Mode

23.5.1

Transition to Sleep Mode

When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep

mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are

retained. Other peripheral functions do not stop.

23.5.2

Clearing Sleep Mode

Sleep mode is exited by any interrupt, signals on the

RES or STBY pin, and a reset caused by a

watchdog timer overflow.

1. Clearing by interrupt

When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep

mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the

CPU.

2. Clearing by

RES pin

Setting the

RES pin level low selects the reset state. After the stipulated reset input duration,

driving the

RES pin high makes the CPU start the reset exception processing.

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