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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663M 数据表(PDF) 539 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 539 Page - Renesas Technology Corp |
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539 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 507 of 1468 REJ09B0412-0200 EXDMA byte read cycle EXDMA byte read cycle EXDMA word read cycle EXDMA word write cycle EXDMA word write cycle EXDMA byte read cycle EXDMA byte read cycle EXDMA word read cycle EXDMA word write cycle EXDMA word write cycle Address bus B φ RD LLWR LHWR TEND Bus released Bus released Bus released Last transfer cycle m and n are integers. 4m + 1 4m + 2 4m + 4 4n + 4 4n + 6 4n 4n + 2 4m + 5 4m + 6 4m + 8 Figure 11.25 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer (Transfer Source EDSAR = Odd Address, Source Address Incremented) EXDMA word read cycle EXDMA word read cycle EXDMA byte write cycle EXDMA byte write cycle EXDMA byte write cycle EXDMA word write cycle EXDMA word read cycle EXDMA word read cycle EXDMA byte write cycle EXDMA word write cycle Address bus B φ RD LLWR LHWR ETEND Bus released Bus released Bus released Last transfer cycle m and n are integers. 4n + 5 4m + 2 4m 4n + 6 4n + 8 4n + 4 4m + 4 4m + 6 4n + 1 4n + 2 Figure 11.26 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer (Transfer Destination EDDAR = Odd Address, Destination Address Decremented) |
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