H8SXSLASH1663M datasheet(1073/1504 Pages) RENESAS

1073 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1041 of 1468

REJ09B0412-0200

21.3.3

2C Bus Mode Register (ICMR)

ICMR selects MSB first or LSB first, controls the master mode wait and selects the number of

transfer bits.

Bit

Bit Name

Initial Value

R/W



R/W

WAIT

R/W



BCWP

R/W

BC2

R/W

BC1

R/W

BC0

R/W

Bit

Bit Name

Initial

Value

R/W

Description



R/W

Reserved

The write value should always be 0.

WAIT

R/W

Wait Insertion

This bit selects whether to insert a wait after data

transfer except for the acknowledge bit. When this bit is

set to 1, after the falling of the clock for the last data bit,

the low period is extended for two transfer clocks.

When this bit is cleared to 0, data and the acknowledge

bit are transferred consecutively with no waits inserted.

The setting of this bit is invalid in slave mode.



Reserved

These bits are always read as 1.

BCWP

R/W

BC Write Protect

This bit controls the modification of the BC2 to BC0

bits. When modifying, this bit should be cleared to 0

and the MOV instruction should be used.

0: When writing, the values of BC2 to BC0 are set

1: When reading, 1 is always read

When writing, the settings of BC2 to BC0 are invalid.

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