R4F2189R datasheet(62/812 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Aug. 03, 2005 Page 20 of 766

REJ09B0223-0200

2.2

CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode* supports a

maximum 64 Kbytes address space. Advanced mode supports a maximum 16 Mbytes address

space. The mode is selected by the LSI's mode pins.

Note: * Not available in this LSI.

2.2.1

Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU in normal

mode.

• Address space

Linear access to a maximum address space of 64 Kbytes is possible.

• Extended registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers.

When extended register En is used as a 16-bit register it can contain any value, even when the

corresponding general register (Rn) is used as an address register. (If general register Rn is

referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-

increment (@Rn+) and a carry or borrow occurs, the value in the corresponding extended

• Instruction set

All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

• Exception vector table and memory indirect branch addresses

In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. The exception vector table in normal mode is shown in

figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,

providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000

to H'00FF. Note that this area is also used for the exception vector table.

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