R4F2189R datasheet(13/812 Pages) RENESAS

13 / 812 page

Rev. 2.00 Aug. 03, 2005 Page xiii of xlii

5.3.4

IRQ Status Registers (ISR16, ISR) ......................................................................... 86

5.3.5

Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)

Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB) ....................... 88

5.3.6

IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register

(ISSR) ..................................................................................................................... 92

5.4

Interrupt Sources.................................................................................................................. 94

5.4.1

External Interrupt Sources ...................................................................................... 94

5.4.2

Internal Interrupt Sources ....................................................................................... 97

5.5

Interrupt Exception Handling Vector Tables ....................................................................... 98

5.6

Interrupt Control Modes and Interrupt Operation .............................................................. 105

5.6.1

Interrupt Control Mode 0 ...................................................................................... 108

5.6.2

Interrupt Control Mode 1 ...................................................................................... 110

5.6.3

Interrupt Exception Handling Sequence ............................................................... 113

5.6.4

Interrupt Response Times ..................................................................................... 115

5.7

Usage Notes ....................................................................................................................... 116

5.7.1

Conflict between Interrupt Generation and Disabling .......................................... 116

5.7.2

Instructions for Disabling Interrupts ..................................................................... 117

5.7.3

Interrupts during Execution of EEPMOV Instruction........................................... 117

5.7.4

Vector Address Switching .................................................................................... 117

5.7.5

External Interrupt Pin in Software Standby Mode and Watch Mode.................... 118

5.7.6

Noise Canceller Switching.................................................................................... 118

5.7.7

IRQ Status Register (ISR)..................................................................................... 118

Section 6 Bus Controller (BSC).........................................................................119

6.1

Register Descriptions ......................................................................................................... 119

6.1.1

Bus Control Register (BCR) ................................................................................. 119

6.1.2

Wait State Control Register (WSCR) ................................................................... 120

Section 7 I/O Ports .............................................................................................121

7.1

Port 1.................................................................................................................................. 126

7.1.1

Port 1 Data Direction Register (P1DDR).............................................................. 126

7.1.2

Port 1 Data Register (P1DR)................................................................................. 127

7.1.3

Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 127

7.1.4

Pin Functions ........................................................................................................ 128

7.1.5

Port 1 Input Pull-Up MOS .................................................................................... 128

7.2

Port 2.................................................................................................................................. 129

7.2.1

Port 2 Data Direction Register (P2DDR).............................................................. 129

7.2.2

Port 2 Data Register (P2DR)................................................................................. 130

7.2.3

Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 130

7.2.4

Pin Functions ........................................................................................................ 131

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