SH7052 datasheet(13/919 Pages) RENESAS

13 / 919 page

iii

6.3.3

IRQ Status Register (ISR) ....................................................................................

6.4

Interrupt Operation ............................................................................................................

6.4.1

Interrupt Sequence................................................................................................

6.4.2

Stack after Interrupt Exception Processing ..........................................................

6.5

Interrupt Response Time ...................................................................................................

6.6

Data Transfer with Interrupt Request Signals ...................................................................

6.6.1

Handling CPU Interrupt Sources, but Not DMAC Activating Sources ...............

6.6.2

Handling DMAC Activating Sources but Not CPU Interrupt Sources ................

Section 7

User Break Controller (UBC) ..................................................................... 99

7.1

Overview............................................................................................................................

7.1.1

Features ................................................................................................................

7.1.2

Block Diagram...................................................................................................... 100

7.1.3

7.2

Register Descriptions......................................................................................................... 101

7.2.1

User Break Address Register (UBAR)................................................................. 101

7.2.2

User Break Address Mask Register (UBAMR) ................................................... 102

7.2.3

User Break Bus Cycle Register (UBBR) ............................................................. 104

7.2.4

User Break Control Register (UBCR).................................................................. 106

7.3

Operation ........................................................................................................................... 107

7.3.1

Flow of the User Break Operation........................................................................ 107

7.3.2

Break on On-Chip Memory Instruction Fetch Cycle ........................................... 109

7.3.3

Program Counter (PC) Values Saved ................................................................... 109

7.4

Examples of Use................................................................................................................ 110

7.4.1

Break on CPU Instruction Fetch Cycle ................................................................ 110

7.4.2

Break on CPU Data Access Cycle........................................................................ 111

7.4.3

Break on DMA Cycle ........................................................................................... 111

7.5

Usage Notes ....................................................................................................................... 112

7.5.1

Simultaneous Fetching of Two Instructions......................................................... 112

7.5.2

Instruction Fetch at Branches ............................................................................... 112

7.5.3

Contention between User Break and Exception Processing ................................ 113

7.5.4

Break at Non-Delay Branch Instruction Jump Destination.................................. 113

7.5.5

User Break Trigger Output ................................................................................... 113

7.5.6

Module Standby.................................................................................................... 114

Section 8

Bus State Controller (BSC) ......................................................................... 115

8.1

Overview............................................................................................................................ 115

8.1.1

Features ................................................................................................................ 115

8.1.2

Block Diagram...................................................................................................... 116

8.1.3

Pin Configuration ................................................................................................. 117

8.1.4

8.1.5

Address Map ........................................................................................................ 118

8.2

Description of Registers .................................................................................................... 122

SH7052 数据表(PDF) 13 Page - Renesas Technology Corp

SH7052 数据表(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载