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SH7713 数据表(PDF) 39 Page - Renesas Technology Corp |
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SH7713 数据表(HTML) 39 Page - Renesas Technology Corp |
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39 / 904 page ![]() Rev.1.50 Aug. 30, 2006 Page xxxix of xl Table 16.2 Relationship between n and Clock........................................................................ 553 Table 16.3 SCSMR Settings for Serial Transfer Format Selection......................................... 560 Table 16.4 SCSMR and SCSCR Settings for the SCIF Clock Source Selection .................... 560 Table 16.5 Serial Transfer Formats......................................................................................... 562 Table 16.6 The SCIF Interrupt Sources .................................................................................. 583 Section 17 Serial I/O with FIFO (SIOF) Table 17.1 Pin Configuration.................................................................................................. 589 Table 17.2 SIOF Serial Clock Frequency ............................................................................... 614 Table 17.3 Serial Transfer Modes........................................................................................... 616 Table 17.4 Frame Length........................................................................................................ 617 Table 17.5 Audio Mode Specification for Transmit Data....................................................... 619 Table 17.6 Audio Mode Specification for Receive Data ........................................................ 619 Table 17.7 Setting for Number of Control Data Channels...................................................... 620 Table 17.8 Conditions to Issue Transmit Request .................................................................. 622 Table 17.9 Conditions to Issue Receive Request .................................................................... 622 Table 17.10 Transmission and Reception Reset ................................................................... 628 Table 17.11 SIOF Interrupt Sources ..................................................................................... 629 Table 17.12 Setting Condition of Transmit/Receive Interrupt Flag...................................... 630 Section 18 Ethernet Controller (EtherC) Table 18.1 Pin Configuration.................................................................................................. 638 Section 20 Pin Function Controller (PFC) Table 20.1 List of Multiplexed Pins (1).................................................................................. 719 Table 20.2 List of Multiplexed Pins (2).................................................................................. 720 Section 21 I/O Ports Table 21.1 Port A Data Register (PADR) Read/Write Operations ......................................... 728 Table 21.2 Port B Data Register (PBDR) Read/Write Operations (1).................................... 729 Table 21.3 Port B Data Register (PBDR) Read/Write Operations (2).................................... 729 Table 21.4 Port C Data Register (PCDR) Read/Write Operations.......................................... 730 Section 22 User Debugging Interface (H-UDI) Table 22.1 Pin Configuration.................................................................................................. 732 Table 22.2 H-UDI Commands................................................................................................ 734 Table 22.3 This LSI’s Pins and Boundary Scan Register Bits................................................ 735 Table 22.4 Reset Configuration .............................................................................................. 743 Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings ................................................................................. 783 Table 24.2 DC Characteristics (1)........................................................................................... 785 Table 24.2 DC Characteristics (2)........................................................................................... 786 |
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