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SH7713 数据表(PDF) 86 Page - Renesas Technology Corp

部件名 SH7713
功能描述  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SH7713 数据表(HTML) 86 Page - Renesas Technology Corp

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Section 2 CPU
Rev.1.50 Aug. 30, 2006 Page 46 of 860
REJ09B0288-0150
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation Formula
Register
indirect with
pre-decrement
@–Rn
Effective address is register Rn
contents, decremented by a constant
beforehand: 1 for a byte operand, 2 for a
word operand, 4 for a longword
operand.
Rn
Rn - 1/2/4
1/2/4
-
Rn - 1/2/4
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Longword: Rn – 4
→ Rn
(Instruction executed with
Rn after calculation)
Register
indirect with
displacement
@(disp:4,
Rn)
Effective address is register Rn contents
with 4-bit displacement disp added. After
disp is zero-extended, it is multiplied by
1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Rn
Rn
+ disp
× 1/2/4
1/2/4
+
disp
(zero-extended)
×
Byte: Rn + disp
Word: Rn + disp
× 2
Longword: Rn + disp
× 4
Indexed
register indirect
@(R0, Rn)
Effective address is sum of register Rn
and R0 contents.
+
Rn
R0
Rn + R0
Rn + R0
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR
contents with 8-bit displacement disp
added. After disp is zero-extended, it is
multiplied by 1 (byte), 2 (word), or 4
(longword), according to the operand
size.
GBR
GBR
+ disp
× 1/2/4
1/2/4
+
disp
(Zero-extended)
×
Byte: GBR + disp
Word: GBR + disp
× 2
Longword: GBR + disp
×
4



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