M38047FEHKP datasheet(184/387 Pages) RENESAS

184 / 387 page

2-60

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

2.4.6 Serial I/O pin function and selection method

(1)

Serial I/O1, serial I/O3

Table 2.4.1 shows the pin function in the clock synchronous serial I/O mode, Table 2.4.2 shows the

pin function in the UART mode.

Table 2.4.1 Pin function in clock synchronous serial I/O mode

Pin name

(Serial I/O1)

P44/RxD1

P45/TxD1

P46/SCLK1

P47/SRDY1

/CNTR2

Function

RxD1, RxD3

P44, P34

TxD1, TxD3

P45, P35

SCLK1 (External clock input)

SCLK1 (Internal clock output)

SRDY1, SRDY3

P47, P37

SIOE

SIOM

TIC

SRDYSCS

CSS

Serial I/O1 control register (address 001A16)

Serial I/O3 control register (address 003216)

b6b5b4b3b2b1b0

✕✕✕

✕✕

✕✕✕

✕✕

Note 1: When SIOE is set to “0”, all pins become I/O ports regardless of set value of b6–b0.

Note 2: In the pulse output mode, the programmable waveform generating mode, or the programmable one-shot generating mode of

the timer Z, this pin functions as the timer Z function output pin regardless of b7-b0 setting.

✕: This is not used for the pin’s function setting.

Corre-

sponding

direction

0/1

(Note 1)

Pin name

(Serial I/O3)

P34/RxD3

P35/TxD3

P36/SCLK3

P37/SRDY3

(Note 2)

Table 2.4.2 Pin function in UART mode

RxD

P44

TxD

P45

SCLK1 (External clock input)

P46

P47

SIOE

SIOMRE

TIC

SRDYSCS

CSS

b4b3

b1b0

✕✕✕

✕✕

Corre-

sponding

direction

0/1

Function

Serial I/O1 control register (address 001A16)

Note 1: When SIOE is set to “0”, all pins become I/O ports regardless of set value of b6–b0.

Note 2: In the pulse output mode, the programmable waveform generating mode, or the programmable one-shot generating mode of

the timer Z, this pin functions as the timer Z function output pin regardless of b7-b0 setting.

✕: This is not used for the pin’s function setting.

Pin name

(Serial I/O1)

P44/RxD1

P45/TxD1

P46/SCLK1

P47/SRDY1

/CNTR2

Pin name

(Serial I/O3)

P34/RxD3

P35/TxD3

P36/SCLK3

P37/SRDY3

(Note 2)

(Note 1)

Table 2.4.3 Pin function in clock synchronous serial I/O mode

P50/SIN2

P51/SOUT2

P52/SCLK2

P53/SRDY2

SIN2

P50

SOUT2

SCLK2 (External clock input)

SCLK2 (Internal clock output)

SRDY2

P53

b7b6b5b4b3

b2b1b0

✕✕✕

✕✕

Notes 1: Although this pin functions as SIN2 when b3 is set to “0”, set “1” to b3.

Notes 2: Although this pin functions as SCLK2 when b3 and the corresponding direction register are set to “0”, set “1” to b3.

Notes 3: When the corresponding direction register bit is "1", the b7 setting is valid.

✕: This is not used for the pin’s function setting.

P52

0/1

(Note 1)

Pin name

Function

Serial I/O2 control register (address 001D16)

Correspond-

ing direction

(Note 2)

P51

✕✕✕

(Note 3)

✕✕

0/1

CMOS output

N-channel open-drain output

(2)

Serial I/O2

Table 2.4.3 shows the pin function in the clock synchronous serial I/O mode.

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