M38047FEHKP datasheet(188/387 Pages) RENESAS

188 / 387 page

2-64

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Figure 2.4.23 shows a control procedure of the transmitting side, and Figure 2.4.24 shows a control

procedure of the receiving side.

Fig. 2.4.23 Control procedure of transmitting side

RESET

Initialization

(Address : 001A16)

(Address : 001C16)

(Address : 003A16), bit1

SIO1CON

BRG1

INTEDGE

8 – 1

TB1/RB1

(Address : 001816)

The first byte of a

transmission data

• Transmission data write

Transmit buffer empty flag is set to “0”

by this writing.

• Detection of INT1 falling edge

IREQ1 (Address: 003C16), bit1?

• Judgment of transferring from Transmit

buffer register to Transmit shift register

(Transmit buffer empty flag)

SIO1STS (Address : 001916), bit0?

TB1/RB1

(Address : 001816)

• Transmission data write

Transmit buffer empty flag is set to “0”

by this writing.

The second byte of a

transmission data

• Judgment of transferring from Transmit

buffer register to Transmit shift register

(Transmit buffer empty flag)

SIO1STS (Address : 001916), bit0?

• Judgment of shift completion of Transmit shift register

(Transmit shift register shift completion flag)

SIO1STS (Address : 001916), bit2?

IREQ1 (Address : 003C16), bit1

1101xx002

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

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