M38047FEHKP datasheet(191/387 Pages) RENESAS

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2-67

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Serial I/O1 synchronous clock : BRG/4

SRDY1

output disabled

Serial I/O1 transmit interrupt : Disabled

ICON1

Interrupt control register 1 (Address : 003E16)

Serial I/O1 transmit interrupt request

Confirm completion of transmitting

1-byte data by one unit.

“1” : Transmit shift completion

IREQ1

Interrupt request register 1 (Address : 003C16)

SIO1CON

Serial I/O1 control register (Address : 001A16)

BRG count source : f(XIN)

Transmit interrupt source : Transmit shift operating completion

Transmit enabled

Receive disabled

Clock synchronous serial I/O

Serial I/O1 enabled

P45/TXD1 pin : CMOS output

UART1CON

UART1 control register (Address : 001B16)

8 – 1

Set “division ratio – 1”

BRG1

Baud rate generator 1 (Address : 001C16)

Port P6 (Address : 000C16)

Port P63: Output mode

P6D

Port P6 direction register (Address : 000D16)

Port P63: CS signal to peripheral ICs

"L" active

Figure 2.4.27 shows registers setting relevant to serial I/O1, and Figure 2.4.28 shows a setting of

serial I/O1 transmission data.

Fig. 2.4.27 Registers setting relevant to serial I/O1

Set a transmission data.

Confirm that transmission of the previous data is

completed (bit 3 of the Interrupt request register 1

is “1”) before writing data.

TB1/RB1

Transmit/Receive buffer register 1 (Address : 001816)

Fig. 2.4.28 Setting of serial I/O1 transmission data

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