M38047FEHKP datasheet(187/387 Pages) RENESAS

187 / 387 page

2-63

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.4.22 Registers setting relevant to receiving side

Receiving side

Serial I/O1 control register (Address : 001A16)

SIO1CON

Serial I/O1 synchronous clock : External clock

SRDY1

output enabled

Transmit enabled

Set this bit to “1”, using SRDY1 output.

Receive enabled

Clock synchronous serial I/O

Serial I/O1 enabled

Serial I/O1 status register (Address : 001916)

SIO1STS

Receive buffer full flag

Confirm completion of receiving 1-byte data with this flag.

“1” : at completing reception

“0” : at reading out contents of Receive buffer register

Overrun error flag

“1” : When data is ready in Receive shift register while Receive buffer

Parity error flag

“1” : When a parity error occurs in enabled parity.

Framing error flag

“1” : When stop bits cannot be detected at the specified timing

Summing error flag

“1” : when any one of the following errors occurs.

• Overrun error

• Parity error

• Framing error

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