M38047FEHKP datasheet(195/387 Pages) RENESAS

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2-71

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

(3)

Cyclic transmission or reception of block data (data of specified number of bytes) between

two microcomputers

Outline : When the clock synchronous serial I/O is used for communication, synchronization of the

clock and the data between the transmitting and receiving sides may be lost because of

noise included in the synchronous clock. It is necessary to correct that constantly, using

“heading adjustment”.

This “heading adjustment” is carried out by using the interval between blocks in this

example. This example is described for serial I/O1, but this example also can apply serial

I/O3.

Figure 2.4.33 shows connection diagram.

Fig. 2.4.33 Connection diagram

Specifications :

• Serial I/O is used (clock synchronous serial I/O is selected).

• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)

• Byte cycle: 488

µs

• Number of bytes for transmission or reception : 8 byte/block

• Block transfer cycle : 16 ms

• Block transfer term : 3.5 ms

• Interval between blocks : 12.5 ms

• Heading adjustment time : 8 ms

Limitations of the specifications :

• Reading of the reception data and setting of the next transmission data must be

completed within the time obtained from “byte cycle – time for transferring 1-byte

data” (in this example, the time taken from generating of the serial I/O1 receive

interrupt request to input of the next synchronous clock is 431

µs).

•“Heading adjustment time < interval between blocks” must be satisfied.

SCLK1

Master unit

SCLK1

Slave unit

TXD1

RXD1

TXD1

RXD1

Note: Use SOUT2 and SIN2 instead of TxD1 and RxD1 for serial I/O2.

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