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M38047FEHKP 数据表(PDF) 201 Page - Renesas Technology Corp

部件名 M38047FEHKP
功能描述  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  387 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M38047FEHKP 数据表(HTML) 201 Page - Renesas Technology Corp

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APPLICATION
2.4 Serial interface
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3804 Group (Spec.H)
Serial I/O1 status register (Address : 001916)
SIO1STS
Transmitting side
Baud rate generator 1 (Address : 001C16)
BRG1
8 – 1
SIO1CON 1
00 1
0 1
0
UART1 control register (Address : 001B16)
UART1CON
0
01
0
f(XIN)
Transfer bit rate ✕ 16 ✕ m
–1
b7
b0
Serial I/O1 control register (Address : 001A16)
b7
b0
b7
b0
b7
b0
Set
When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,”
a value of m is 1.
When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,”
a value of m is 4.
BRG count source : f(XIN)/4
Synchronous clock : BRG/16
Transmit enabled
Receive disabled
Asynchronous serial I/O(UART)
Serial I/O1 enabled
SRDY1
output disabled
Character length : 8 bits
Parity checking disabled
P45/TXD1 pin : CMOS output
Stop bit length : 2 stop bits
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Port P40: Communication control: “H” active
P4
Port P4 (Address : 000816)
0
b7
b0
Port P40: Communication control: Output mode
P4D
Port P4 direction register (Address : 000916)
1
b7
b0
Fig. 2.4.40 Registers setting relevant to transmitting side



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