M38047FEHKP datasheet(202/387 Pages) RENESAS

202 / 387 page

2-78

APPLICATION

2.4 Serial interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Receiving side

Serial I/O1 status register (Address : 001916)

SIO1STS

BRG1

8 – 1

Serial I/O1 control register (Address : 001A16)

SIO1CON

UART1CON

UART1 control register (Address : 001B16)

Character length : 8 bits

Parity checking disabled

Stop bit length : 2 stop bits

Baud rate generator 1 (Address : 001C16)

f(XIN)

Transfer bit rate ✕ 16 ✕ m

–1

Set

When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,”

a value of m is 1.

When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,”

a value of m is 4.

✽

BRG count source : f(XIN)/4

Synchronous clock : BRG/16

Transmit disabled

Receive enabled

Asynchronous serial I/O(UART)

Serial I/O1 enabled

SRDY1

output disabled

Receive buffer full flag

Confirm completion of receiving 1-byte data with this flag.

“1” : at completing reception

“0” : at reading out contents of Receive buffer register

Overrun error flag

“1” : When data is ready in Receive shift register while Receive buffer

Parity error flag

“1” : When a parity error occurs in enabled parity.

Framing error flag

“1” : When stop bits cannot be detected at the specified timing

Summing error flag

“1” : when any one of the following errors occurs.

• Overrun error

• Parity error

• Framing error

Port P40: Communication control: Input mode

P4D

Port P4 direction register (Address : 000916)

Fig. 2.4.41 Registers setting relevant to receiving side

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