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TDA7326 数据表(PDF) 9 Page - STMicroelectronics |
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TDA7326 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 16 page ![]() 3.5 THREE STATE PHASE COMPARATOR The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator 3.6 CHARGE PUMP CURRENT GENERATOR This system generates signed pulses of current. Duration and polarity of those pulses are deter- mined by the phase error signal. The absolute current values are programmable by ’CURR1’ and ’CURR2’ bits and controlled by an external resistor RISET connected to Pin 2 and GND. 3.7 LOW NOISE CMOS OP-AMP A low noise Op-Amp is available on chip. The positive input of this Op-Amp is connected to an internal voltage divider and to Pin 3 ’VREF’. The negative input is connected to the charge pump output. In cooperation with this internal amplifier and external components, an active filter can be provided. To increase the flexibility in application the negative input can be switched to two input pins (Pins 15 and 16). This switch is controlled by ’LPF’ register with ’LPF’ low Pin 15 is active and ’LPF’ high Pin 16 is active. This feature allows two separate active filters with different perform- ance. 3.8 TEST FUNCTION The test pin (Test Out) is used only for testing: it has no use in real applications. The three bits test0, test1, test2, of the test REGISTER must be programmed as 0,0,0 in application. Some device internal signals can be checked at pin 9 (TST OUT) and pin 7 (OSC IN) by program- ming different codes of the test register according to the Table 1. For example by programming the code 110 the ”fsyn out” will be available at pin 9 and ”fREF in- put” at pin 7. 3.9 C-BUS INTERFACE This interface allows communication between the PLL device and µp systems. A bus control system check the format of transmission, only eight bit word transmission is allowed. Four registers with 6 bit are user programmable. The selection of this four registers is controlled by two address bits. Test Register Status Test Function test 0 test 1 test 2 PIN9 (TEST/OUT) PIN 7 (OSCIN) 00 0 Sout (appl. mode) Oscin (appl. mode) 10 0 fref Output Oscin (appl. mode) 01 0 Phi Output fref Input 11 0 fsyn Output fref Input 00 1 Phi input Oscin (appl. mode) TABLE 1: TDA7326 9/16 |
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