TDA7421 datasheet(16/38 Pages) STMICROELECTRONICS

16 / 38 page

quency. In FM mode a 6.25 KHz, in AM mode a

1KHz signal is generated. This counter is fol-

lowed by an asynchronous divider to generate

several sampling times.

Intermediate Frequency Main Counter (IFMC)

This counter is a 13-21 bit synchronous autore-

load down-counter. Four bits are programmable

to have the possibility for an adjust to the fre-

quency of the IF filter.

The counter length is automatically adjusted to

the chosen sampling time and the counter mode.

At the start the counter will be loaded with a de-

fined value which is an equivalent to the divider

value (tsample fIF).

If a correct frequency is applied to the IF counter

frequency inputs IF-AM and IF-FM, at the end of

the sampling time the main counter is changing

its state from 0 to 1FFFFFH.

This is detected by a control logic. The frequency

range inside which a successful count results is

detected is adjustable setting bits EW 0, 1, 2.

Up-down counter filter

The information coming from the IF main counter

control logic is shifted into a 5 bit up down

counter circuit clocked by the sampling time sig-

nal. At the start (rising edge of the IFENA signal)

the counter is set to 10H and the SSTOP signal is

forced to "1".

Only when the counter reaches the value 10H -

step, SSTOP goes to "0".

SSTOP will be "1" again, if the counter reaches

the value 10h + step.

MSB

LSB

FUNCTION

SUBAD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PLL CHARGE PUMP

00H

L P IN1/2

CURRH

PLL COUNTER

01H

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PLL COUNTER

02H

PC15

PC14

PC13

PC12

PC11

PC10

PC9

PC8

PLL REF

COUNTER

03H

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

PLL REF

COUNTER

04H

RC15

RC14

RC13

RC12

RC11

RC10

RC9

RC8

PLL LOCK

DETECT

05H

LDENA

PM1

PM0

IFC REF COUNTER

06H

IRC7

IRC6

IRC5

IRC4

IRC3

IRC2

IRC1

IRC0

IFC REF COUNTER

07H

IFCM1

IFCM0

IRC13

IRC12

IRC11

IRC10

IRC9

IRC8

IFC CONTROL

08H

IFENA

EW2

EW1

EW0

IFC CONTROL

09H

IFS2

IFS1

IFS0

CF4

CF3

CF2

CF1

CF0

ADDRESS ORGANIZATION (PLL and IF Counter)

REF OSC IN

R0 ...R15

DIVIDER

: R

AM IN

FM IN

PC0 ...PC4

COUNTER

PRESCALER

32/33

PC5 ... P15

DIVIDER

: B

fref

fsyn

D96AU545

fosc

2C bus

(O/I)

FM and AM operation (swallow mode)

CURR HIGH

LOCKENA

LOCK

CHARGE PUMP

CURRENT

D96AU548

Charge Pump Logic

TDA7421

16/38

TDA7421 数据表(PDF) 16 Page - STMicroelectronics

TDA7421 数据表(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

数据表下载

链接网址

TDA7421 数据表(PDF) 16 Page - STMicroelectronics

TDA7421 数据表(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

数据表 下载

链接网址

数据表下载