POWER CONSUMPTION

Symbol

Parameter

Value

Unit

Maximum current for core power supply @ 3.3V

320

mA

Note: 40MHz internal DSP clock at Tamb

EXTERNAL CLOCKS (XTI Pin)

The TDA7503 system clock is externally supplied via the XTI pin.

Timings shown in this document are valid for clock rise and fall times of 3ns maximum.

Symbol

Characteristics

Value

Unit

Max. Frequency @ XTI when PLL is disabled

20

MHz

When PLL is enabled see constraints for Internal Clocks.

INTERNAL CLOCKS

Symbol

Characteristics

Expression

Maximum DSP Internal Operation Frequency (dclk)

40MHz

Maximum

µP (8051) Internal Operation Frequency (mclk)

20MHz

Internal DSP Clock Cycle Frequency (dclk)

MF

2

⋅ DF

Inernal

µP (8051) Clock Cycle Frequency (mclk)

MF

4

⋅ DF

DSP Machine Cycle Time

dclk

µP (8051) Machine Cycle Time

mclk/12

Note 1: If the DCKSRC bit of the clock control register is 0 then dclk = Fext/2.

Note 2: If the MCKSRC bit of the clock control register is 1 then mclk = Fext else of MCKSRC0 is 0 then MC LK = Fext/4.

Note 3: DF is PLL input devide factor, bits IDF [4:0] of PLL control register one.

Note 4: MF is PLL multiply devide factor, bits MP [6:0] of PLL control register zero.

PHASE LOCKED LOOP (PLL) CHARACTERISTICS

Characteristics

Expression

Value

Unit

VCO frequency when PLL enabled

MF

⋅ Fext

DF

40 to 80

MHz

Recommended PLL external capacitor (pin

FILT)

3.3

nF

RESET

Characteristics

Expression

Unit

Minimum RESET assertion

100/Fext

ns

TDA7503

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