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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TDA7503 数据表(PDF) 10 Page - STMicroelectronics |
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TDA7503 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 26 page  TDE LRCKT Left Right Left Right Internal Flag set when left data written to all enabled transmitters. If this internal TDE cleared when right data written to all enabled transmitters. flag is set then right data must written to data registers before the next RDR LRCKR Left Right Left Right RDR cleared when right data read from all enabled transmitters. Internal Flag set when left data read from all enabled receivers. If this internal flag is set then right data must read from data registers before the next falling edge of LRCKT. rising edge of LRCKR. Figure 2. SAI Interrupt protocol SDI0-3 LRCKR SCKR (RCKP=0) tlrh tsdis tsdih tlrs t sckpl tsckph Valid Valid tdt t sckr SAI/SSI INTERFACE Figure 1. SAI and SSI Timings Timing Description Value Unit tsckr Minimum Clock Cycle 3TDSP+5 ns tdt SCKR active edge to data out valid 40 ns tlrs LRCK setup time 5 ns tlrh LRCK hold time 5 ns tsdid SDI setup time 5 ns tsdih SDI hold time 5 ns tsckph Minimum SCK high time 0.35 tsckr ns tsckpl Minimum SCK low time 0.35 tsckr ns Note TDSP = dsp master clock cycle time = 1/FDSP TDA7503 10/26 |
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