addressable DRAM

– Refresh rate for DRAM can be chosen

among sixteen divide factors

– SRAM or DRAM relative addressing modes

– 2

– Four SRAM Timing choices

– Two Read Offset Register

PLL

The Euterpe clock system generates the fol-

lowing clocks:

– DCLK

the DSP core clock

– MCLK

CODEC master clock

– LRCLK

left/right clock for the SAI and

the CODEC

– SCLK

shift serial clock for the SAI and

the CODEC

The output of the PLL operates from 70 to 140

MHz. The DSP core can operate with a clock

up to 50 MHz.

From the VCO output the audio clock are de-

rived.

CODEC

The main features of the CODEC are listed be-

low:

– one 16-bit Delta Sigma Stereo ADC

– 80 dB Dynamic Range

– Oversampling Ratio: 128

– one 16-bit Delta Sigma Stereo DAC

– 80 dB Dynamic Range

– Interpolating Ratio: 128

– Sampling rates of 4kHz to 48kHz

– Signal Noise Ratio: 80 dB Typ.

The analog interface is in the form of differen-

tial signals for each channel. The interface on

the digital side has the form of an SAI interface

and can interface directly to an SAI channel

and then to the DSP core.

DEVICE versions

Part No.

Internal

Program

Memory

Function

Serial I/F

External

Memory

Audio

Input

Audio

Output

Software

TDA7550R

RAM

One of the

below

Master or

Slave I

FLASH

or RAM

YES

(by appl.)

YES

(by appl.)

Custom

Specs.

TDA7550

ROM

Speech

Recognition

Slave I

FLASH

YES, 1

(voice in)

YES

(prompts)

ASR-311

Engine by

Lernout &

Hauspie

TDA7551

Speaker

Verification

Slave I

Optional

FLASH

YES, 1

(voice in)

YES

(prompts)

SV208

Engine by

Lernout &

Hauspie

TDA7552

Text-To-

Speech

Slave I

–

NO

YES

(voice out)

TTS3000

Engine by

Lernout &

Hauspie

TDA7553

SF/FDE

Master

I

(RAM)

YES, 1

(voice in)

YES

(filtered)

Engine by

NCTI

Note: TDA7550 requires word databases on FLASH (cfr. Document words)

TDA7550R - TDA7550 - TDA7551 - TDA7552 - TDA7553

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