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TDA7580

DSP PERIPHERALS

The peripherals are mapped in the X-memory space.

Most of them can be handled by interrupt, with software programmable priority.

Peripherals running at very high rate have direct access to X and Y Data Bus for very fast movement from or to

the core, by mean of single cycle instruction.

CLOCK GENERATION UNIT (CGU) and OSCILLATOR

This unit is responsible for supplying all necessary clocks and synchronization signals to the whole chip.

The control status register of this unit contains information about the current working mode (FM,AM,oscillator

[master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the general setup of the oscillator.

This last function is performed inside the CGU, that establishes -using a self-trimming algorithm- which is the

current that can bias the oscillator: this feature let the oscillator be independent from process parameters vari-

ation. The values of bias current are stored in the control status register of the CGU: 4 bit for the coarse current

steps and 6 bit for the fine current steps. The bits relative to the fine current steps can be anyway corrected

(written) by the DSP to perform the SW frequency trimming (+/-80Hz per step in FM; +/-250Hz in AM).

It sets up the oscillator which works off a quartz crystal of nominally 74.1MHz, generating very low distortion,

thus improving the Electro Magnetic Interference. In FM mode the oscillator generates 74.1MHz, meanwhile in

AM mode this frequency is shifted to 74.106MHz. The quartz characteristics are defined earlier in this document.

In Slave mode the oscillator behaves as a buffer: the chip can be then driven using an external clock. The clock

STEREO DECODER (HWSTER)

The fully digital hardware stereo decoder does all the signal processing necessary to demodulate an FM MPX

signal which is prepared by the channel equalization algorithm in the digital IF sampling device.

It makes up of pilot tone dependent Mono/Stereo switching as well as stereoblend and highcut.

Selectable deemphasis time constant allow the use of this module for different FM radio receiver standards.

There are built-in filters for field strength processing. In order to obtain the maximum flexibility the field strength

processing and noise cancellation, however, are implemented as software inside the programming DSP, which

has to provide control signals for the stages softmute, stereoblend, and highcut.

SERIAL AUDIO INTERFACE (SAI)

The two SAI modules have been embedded in such a way great flexibility is available in their use.

The two modules are fully separate and they each have a Receive and a Transmit channel, as well as they can

be selected as either master or slave.

The bit clocks and Left&Right clocks are routed through the pins, so the audio interface can be chosen to be

adapted to a large variety of application.

One SAI transmit channel can have the Asynchronous Sample Rate Converter in front, thus separate different

audio rate domains.

Additional feature are:

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support of 16/24/32 bit word length

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programmable left/right clock polarity

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programmable rising/falling edge of the bit clock for data valid

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programmable data shift direction, MSB or LSB received/transmitted first