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AD5522JSVDZ 数据表(PDF) 13 Page - Analog Devices

部件名 AD5522JSVDZ
功能描述  Quad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs
PDF  60 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5522JSVDZ 数据表(HTML) 13 Page - Analog Devices

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AD5522
Rev. A | Page 13 of 60
PIN
CLOAD
50pF
VOL
Circuit and Timing Diagrams
TO
OUTPUT
DVCC
RLOAD
2.2k
Ω
Figure 3. Load Circuit for CGALM, TMPALM
VOH(MIN) – VOL(MAX)
2
200µA
IOL
TO OUTPUT
PIN
CLOAD
50pF
200µA
IOH
Figure 4. Load Circuit for SDO, BUSY Timing Diagram
11
2
t3
t2
29
t4
t6
t5
t1
t7
29
SYNC
SCLK
SDI
BUSY
RESET
t8
t9
DB28
DB0
DB28
DB0
t10
t16
t17
BUSY
1LOAD ACTIVE DURING BUSY.
2LOAD ACTIVE AFTER BUSY.
LOAD1
FOHx1
LOAD2
FOHx2
t11
t12
t13
t14
t12
t15
Figure 5. SPI Write Timing (Write Word Contains 29 Bits)



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