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AD5522JSVDZ 数据表(PDF) 21 Page - Analog Devices |
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AD5522JSVDZ 数据表(HTML) 21 Page - Analog Devices |
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21 / 60 page  AD5522 Rev. A | Page 21 of 60 Pin No. Mnemonic Description 46 CPOL2/CPO0 Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. 47 DVCC Digital Supply Voltage. 48 LOAD Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. 49 SDO Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. 50 CPOH1/SDO Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. 51 DGND Digital Ground Reference Point. 52 CPOL1/SYNC Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. 53 SYNC Active Low Frame Synchronization Input for SPI or LVDS Interface. 54 SDI Serial Data Input for SPI or LVDS Interface. 55 CPOH0/SDI Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. 56 CPOL0/SCLK Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. 57 SCLK Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. 58 BUSY Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. 60 EXTFOH2 Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 62 CFF2 External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 63 CCOMP2 Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. 64 EXTMEASIH2 Sense Input (High Sense) for High Current Range (Channel 2). 65 EXTMEASIL2 Sense Input (Low Sense) for High Current Range (Channel 2). 66 FOH2 Force Output for Internal Current Ranges (Channel 2). 67 GUARD2 Guard Output Drive for Channel 2. 68 GUARDIN2/ DUTGND2 Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 69 MEASVH2 DUT Voltage Sense Input (High Sense) for Channel 2. 72 MEASVH0 DUT Voltage Sense Input (High Sense) for Channel 0. 73 GUARDIN0/ DUTGND0 Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 74 GUARD0 Guard Output Drive for Channel 0. 75 FOH0 Force Output for Internal Current Ranges (Channel 0). 76 EXTMEASIL0 Sense Input (Low Sense) for High Current Range (Channel 0). 77 EXTMEASIH0 Sense Input (High Sense) for High Current Range (Channel 0). 78 CCOMP0 Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. 79 CFF0 External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. |
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