ADP5588

Rev. A | Page 23 of 28

Table 44. CMP2_LVL2_TRIP—Register 0x37 (L2 Light Sensor Reference Level (Output Falling for Sensor 2)

Field

Bit

Description

L2_T7 to L2_T0

[7:0]

Sensor 2 comparator Level 2 (Office) reference. If the comparator input is below this trip point, the

comparator trips and enters Level 2 (office) mode and L2_OUT is set. The programmable range is from 0 μA to

1000 μA (0 lux to 2550 lux) in steps of 4 μA.

Table 45. CMP2_LVL2_HYS—Register 0x38 (L2 Light Sensor Hysteresis (Active When Output Rising) for Sensor 2)

Field

Bit

Description

L2_H7 to L2_H0

[7:0]

Sensor 2 comparator Level 2 (Office) hysteresis. If the comparator input is above L2_TRP + L2_HYS, the

comparator trips and enters Level 1 (outdoor) mode and L2_OUT is cleared. The programmable range is from

0 μA to 1000 μA (0 lux to 2550 lux) in steps of 4 μA.

Table 46. CMP2_LVL3_TRIP—Register 0x39 (L3 Light Sensor Reference Level (Output Falling for Sensor 2)

Field

Bit

Description

L3_T7 to L3_T0

[7:0]

Sensor 2 Comparator Level 3 (Dark) Reference. If the comparator input is below L3_TRP, the comparator trips

and enters Level 3 (dark) mode and L3_OUT is set. The programmable range is from 0 μA to 127.5 μA (0 lux to

318.75 lux) in steps of 0.5 μA.

Table 47. CMP2_LVL3_HYS—Register 0x3A (L3 Light Sensor Hysteresis (Active When Output Rising) for Sensor 2)

Field

Bit

Description

L3_H

[7:0]

Sensor 2 comparator Level 3 (Dark) hysteresis. If the comparator input is above L3_TRP + L3_HYS, the

comparator trips and enters Level 2 (office) mode and L3_OUT is cleared. The programmable range is from

0 μA to 127.5 μA (0 lux to 318.75 lux) in steps of -.5 μA.

Table 48. CMP1_ADC_DAT_R1—Register 0x3B (Comparator 1 ADC Data Register 1)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMP1_ADC_DAT

Comparator ADC data register,

Bits[7:0]

NA

NA

NA

ADC12

ADC11

ADC10

ADC9

ADC8

Table 49. CMP1_ADC_DAT_R2—Register 0x3C (Comparator 1 ADC Data Register 2)1

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMP1_ADC_DAT

Comparator ADC data register,

Bits[7:0]

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

Table 50. CMP2_ADC_DAT_R1—Register 0x3D (Comparator 2 ADC Data Register 1)

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMP1_ADC_DAT

Comparator ADC Data Register

[7:0]

N/A

N/A

ADC12

ADC11

ADC10

ADC9

ADC8

Table 51. CMP2_ADC_DAT_R2—Register 0x3E (Comparator 2 ADC Data Register 2)1

Register Name

Register Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMP1_ADC_DAT

Comparator ADC data register,

Bits[7:0]

ADC7

ADC6

ADC5

ADC

ADC3

ADC2

ADC1

ADC0