SSM2319

Rev. 0 | Page 15 of 20

LAYOUT

As output power continues to increase, care must be taken to

lay out PCB traces and wires properly between the amplifier,

load, and power supply. A good practice is to use short, wide

PCB tracks to decrease voltage drops and minimize inductance.

Ensure that track widths are at least 200 mil for every inch of

track length for lowest DCR and use 1 oz or 2 oz of copper PCB

traces to further reduce IR drops and inductance. A poor layout

increases voltage drops, consequently affecting efficiency. Use

large traces for the power supply inputs and amplifier outputs

to minimize losses due to parasitic trace resistance.

Proper grounding guidelines help to improve audio performance,

minimize crosstalk between channels, and prevent switching noise

from coupling into the audio signal. To maintain high output swing

and high peak output power, the PCB traces that connect the

output pins to the load and to the supply pins should be as wide

as possible to maintain the minimum trace resistances. It is also

recommended that a large ground plane be used for minimum

impedances.

In addition, good PCB layouts isolate critical analog paths from

sources of high interference. High frequency circuits (analog

and digital) should be separated from low frequency circuits.

Properly designed multilayer PCBs can reduce EMI emissions

and increase immunity to the RF field by a factor of 10 or more

when compared with double-sided boards. A multilayer board

allows a complete layer to be used for the ground plane, whereas

the ground plane side of a double-sided board is often disrupted

by signal crossover.

If the system has separate analog and digital ground and power

planes, the analog ground plane should be underneath the analog

power plane, and, similarly, the digital ground plane should be

underneath the digital power plane. There should be no overlap

between analog and digital ground planes or analog and digital

power planes.

INPUT CAPACITOR SELECTION

The SSM2319 does not require input coupling capacitors if the

are required if the input signal is not biased within this recom-

mended input dc common-mode voltage range, if high-pass

filtering is needed, or if using a single-ended source. If high-

pass filtering is needed at the input, the input capacitor, along

with the input resistor of the SSM2319, form a high-pass filter

whose corner frequency is determined by

The input capacitor can significantly affect the performance of

the circuit. Not using input capacitors degrades both the output

offset of the amplifier and the PSRR performance.

POWER SUPPLY DECOUPLING

To ensure high efficiency, low THD, and high PSRR, proper

power supply decoupling is necessary. Noise transients on the

power supply lines are short-duration voltage spikes. Although

the actual switching frequency can range from 10 kHz to 100 kHz,

these spikes can contain frequency components that extend into

the hundreds of megahertz. The power supply input needs to be

decoupled with a good quality, low ESL, low ESR capacitor, usually

of around 4.7 μF. This capacitor bypasses low frequency noises

to the ground plane. For high frequency transients noises, use a

0.1 μF capacitor as close as possible to the VDD pin of the device.

Placing the decoupling capacitor as close as possible to the

SSM2319 helps to maintain efficient performance.

SYNCRONIZATION (SYNC) OPERATION

SYNC is the feature that allows an external clock signal to control

the modulator of the SSM2319. The SSM2319 can act in standalone

mode, act as a master device, or act as a slave device. Although

the inherent random switching frequency of the Analog Devices

patented 3-level PDM modulation virtually eliminates the need for

SYNC, this feature can be activated in the event that end users are

concerned about clock intermodulation (beating effect) of several

amplifiers in close proximity.

Another use for the SYNC feature is its ability to adjust modulator

frequency to move harmonic interference to a less sensitive

frequency band in certain applications with very delicate

interference requirements.

Although the synchronization frequency operates from 5 MHz to

12 MHz, the optimal operating range is 6 MHz to 9 MHz.

Modulator synchronization is initiated after the internal shut-

down signal is released. SYNCO buffers the internal oscillator

clock with a delay of 127 clock cycles.

When synchronizing several SSM2319 amplifiers, configure

them in a daisy-chain configuration, as shown in Figure 35.

Using this configuration causes a small delay in the SYNCO-to-

SYNCO transitions of multiple SSM2319s, preventing large

surges of instantaneous current and reducing excessive loading

of the power supply.

When configuring one device to act as a master device, it is

mandatory that the connection from SYNCO to SYCNI be less

than 1 mm. As in many digital systems, to maintain signal integrity

when interfacing several clocking systems, users must insert series

dumping resistors close to the SYNCO pin if long trace lengths

are used for synchronization connections. A typical value used

is 750 Ω. The series dumping resistor should be placed as close

to the SYNCO pin as possible. If careful layout practices are

followed to minimize signal trace routing from the SYNCO pin

of one device to the SYNCI pin of another, a dumping resistor is

not necessary. If the SYNC feature is not used, or if the SYNC

feature is not interfacing the SYNCO pin to an external device,

it is recommended that the SYNCO pin be floated.