TS68230 datasheet(21/61 Pages) STMICROELECTRONICS

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PBCR

H4 Interrupt Enable

The H4 interrupt is disabled.

The H4 interrupt is enabled.

PBCR

H3 SVCRQ Enable

The H3 interrupt and DMA request are disabled.

The H3 interrupt and DMA request are enabled.

PBCR

H3 Status Control

The H3S status bit is set anytime input data is present in the double-buffered input path.

3.3.2. SUBMODE 01 - PIN-DEFINABLE DOUBLE-

BUFFERED OUTPUT OR NON-LATCHED INPUT.

In mode 0, double-buffered output transfers of up to

eight bits are available by programming submode

01 in the desired port’s control register. The opera-

tion of H2 and H4 may be selected by programming

the port A and B control registers, respectively. Da-

ta, written by the bus master to the PI/T, is stored in

the port’s output latches. The peripheral accepts the

data by asserting H1(H3), which causes the next da-

ta to be moved to the port’s output latch as soon as

it is available.

The H1S(H3S) status bit may be programmed for

two interpretations :

1. The H1S(H3S) status bit is set when either the

port initial or final output latch can accept new

data. It is cleared when both latches are full

and cannot accept new data.

2. The H1S(H3S) status bit is set when both of

the port output latches are empty. It is cleared

when at least one latch is full.

The programmable options of the H2(H4) pin are :

1. H2(H4) may be an edge-sensitive input pin in-

dependent of H1(H3) and the transfer of port

data. On the asserted edge of H2(H4), the

H2S(H4S) status bit is set. It is cleared by ei-

ther the RESET pin being asserted, writing a

one to the particular status bit in the port status

(H3(H4) enable) bit of the port general control

2. H2(H4) may be a general-purpose output pin

that is always negated. The H2S(H4S) status

bit is always clear.

3. H2(H4) may be a general-purpose output pin

that is always asserted. The H2S(H4S) status

bit is always clear.

4. H2(H4) may be an output pin in the interlocked

output handshake protocol. H2(H4) is asser-

ted two clock cycles after data is transferred to

the double-buffered output latches. The data

remains stable at the port pins and H2(H4) re-

mains asserted until the next asserted edge of

the H1(H3) input. At that time, H2(H4) is asyn-

chronously negated. As soon as the next data

is available, it is transferred to the output

latches. When H2(H4) is negated, asserted

transitions of H1(H3) have no affect on data

paths. The H2S(H4S) status bit is always clear.

When H12 enable (H34 enable) is clear,

H2(H4) is held negated.

5. H2(H4) may be an output pin in the pulsed out-

put handshake protocol. It is asserted exactly

as in the interlocked protocol above, but never

remains asserted longer than four clock cy-

cles. Typically, a four clock pulse is generated.

But in the case that a subsequent H1(H3) as-

serted edge occurs before termination of the

pulse, H2(H4) is negated asynchronously

shortening the pulse. The H3S(H4S) status bit

is always clear. When H12 enable (H34

enable) is clear H2(H4) is held negated.

For pins used as inputs, data written to the associa-

ted data register is double-buffered and passed to

the initial or final output latch, but, the output buffer

is disabled.

Programmable Options Mode 0 - Port A Submode 00 and Port B Submode 00 (continued)

TS68230

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