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MPC5565 数据表(PDF) 39 Page - Freescale Semiconductor, Inc |
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MPC5565 数据表(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 54 page ![]() Electrical Characteristics MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 39 3.13.7 eMIOS Timing Figure 17. eMIOS Timing 3.13.8 DSPI Timing Table 25. eMIOS Timing 1 1 eMIOS timing specified at: V DDEH = 3.0–5.25 V and TA = TL to TH. Spec Characteristic Symbol Min. Max. Unit 1 eMIOS input pulse width tMIPW 4— tCYC 2 eMIOS output pulse width tMOPW 1 2 2 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR). —tCYC Table 26. DSPI Timing1’ 2 Spec Characteristic Symbol 80 MHz 112 MHz 132 MHz Unit Min. Max. Min. Max. Min. Max. 1 SCK cycle time3, 4 tSCK 24.4 ns 2.9 ms 17.5 ns 2.1 ms 14.8 ns 1.8 ms — 2 PCS to SCK delay5 tCSC 23 — 15 — 13 — ns 3 After SCK delay6 tASC 22 — 14 — 12 — ns 4 SCK duty cycle tSDC (tSCK ÷ 2) – 2 ns (tSCK ÷ 2) + 2 ns (tSCK ÷ 2) – 2 ns (tSCK ÷ 2) + 2 ns (tSCK ÷ 2) – 2 ns (tSCK ÷ 2) + 2 ns ns 5 Slave access time (SS active to SOUT driven) tA — 25 — 25 — 25 ns 6 Slave SOUT disable time (SS inactive to SOUT Hi-Z, or invalid) tDIS — 25 — 25 — 25 ns 7PCSx to PCSS time tPCSC 4— 4 — 4 — ns 8PCSS to PCSx time tPASC 5— 5 — 5 — ns 1 2 eMIOS output eMIOS input |
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