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LPC2103 数据表(PDF) 17 Page - NXP Semiconductors |
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LPC2103 数据表(HTML) 17 Page - NXP Semiconductors |
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17 / 32 page ![]() LPC2101_02_03_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 October 2008 17 of 32 NXP Semiconductors LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (TPCLK × 256 × 4) to (TPCLK × 232 × 4) in multiples of TPCLK × 4. 6.16 Real-time clock The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.16.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra-low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1. The programmable reference clock divider allows fine adjustment of the RTC. • Dedicated power supply pin can be connected to a battery or the main 3.3 V. 6.17 System control 6.17.1 Crystal oscillator On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.17.2 “PLL” for additional information. 6.17.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 µs. |
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