| 数据搜索系统,热门电子元器件搜索 |
|
PCA2002CX8/5/1 数据表(PDF) 7 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCA2002CX8/5/1 数据表(HTML) 7 Page - NXP Semiconductors |
|
7 / 25 page ![]() PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 7 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 7.6 Programming procedure To ensure that the oscillator starts up correctly you must execute a reset sequence (see Figure 4). For a watch it is essential that the timing calibration can be made after the watch is fully assembled. In this situation, the supply pins are often the only terminals which are still accessible. Writing to the OTP cells and performing the related functional checks is achieved in the PCA2002 by modulating the supply voltage. The necessary control circuit consists basically of a voltage level detector, an instruction counter which determines the function to be performed, and an 8-bit shift register which allows writing the OTP cells of an 8-bit word in one step and which acts as data pointer for checking the OTP content. • State 1; measurement of the crystal oscillator frequency (divided by 1024) • State 2; measurement of the inhibition time • State 3; write/check word A • State 4; write/check word B • State 5; check word C (don’t care since no meaning) • State 6; check word D (type recognition) Each instruction state is switched on with a pulse to VP(prog)(start). After this large pulse, an initial waiting time of t0 is required. The programming instructions are then entered by modulating the supply voltage with small pulses (amplitude VP(mod) and pulse width tmod). The first small pulse defines the start time, the following pulses perform three different functions, depending on the time delay (td) from the preceding pulse (see Figure 5, Figure 6, Figure 7, Figure 8 and Figure 9): • td =t1 (0.7 ms); increments the instruction counter • td =t2 (1.7 ms); clocks the shift register with data = logic 0 • td =t3 (2.7 ms); clocks the shift register with data = logic 1 The programming procedure requires a stable oscillator, which means that a waiting time, determined by the start-up time of the oscillator, is necessary after power-up of the circuit. td(start): start delay time. VDD(nom): nominal supply voltage. Fig 4. Supply voltage at start-up during production and testing VDD VP(prog)(stop) td(start) > 500 ms VSS VDD(nom) 001aac503 tp(stop) |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |