PCA2002CX8SLASH5SLASH1 datasheet(8/25 Pages) NXP

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PCA2002_5

Product data sheet

Rev. 05 — 11 November 2008

8 of 25

NXP Semiconductors

PCA2002

32 kHz watch circuit programmable output period and pulse width

After the VP(prog)(start) pulse, the instruction counter is in state 1 and the data shift register

is cleared.

The instruction state ends with a second pulse to VP(prog)(stop) or with the pulse to Vstore.

In any case, the instruction states are terminated automatically 2 seconds after the last

supply modulation pulse.

7.7 Programming the memory cells

Applying the two-stage programming pulse (see Figure 5) transfers the stored data in the

shift register to the OTP cells.

Perform the following to program a memory word:

1. Starting with a VP(prog)(start) pulse, wait for the time period t0 then set the instruction

counter to the word to be written (td =t1).

2. Enter the data to be stored into the shift register (td =t2 or t3), LSB ﬁrst (bit 8) and

MSB last (bit 1).

3. Applying the two-stage programming pulse Vprestore followed by Vstore stores the word.

The delay between the last data bit and the pre-store pulse Vprestore is td =t4. Store

the word by raising the supply voltage to Vstore; the delay between the last data bit and

the store pulse is td.

The example shown in Figure 5 performs the following functions:

• Start

• Setting the instruction counter to state 4 (word B)

• Entering data word 110101 into the shift register (sequence: LSB ﬁrst and MSB last)

• Writing the OTP cells for word B

The example shows the programming of B = 110101 (the sequence is MSB ﬁrst and LSB last).

VDD(nom): nominal supply voltage.

Fig 5.

Supply voltage modulation for programming

mgw356

VDD(nom)

VP(mod)

VDD

VSS

VP(prog)(start)

tp(start)

t1 t1 t1

tw(store)

Vstore

Vprestore

tw(prestore)

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