SAF7115ET datasheet(10/35 Pages) NXP

10 / 35 page

SAF7115_1

Product data sheet

Rev. 01 — 15 October 2008

10 of 35

NXP Semiconductors

SAF7115

Multistandard video decoder

Real time signals

RTCO

(I/) O/st/pd real time control output[6]

RTS1

real time status or sync information, controlled by subaddresses

11h and 12h

RTS0

real time status or sync information, controlled by subaddresses

11h and 12h

Clocks

LLC

line-locked system clock output (27 MHz nominal), for backward

compatibility; use pin XCLK for new applications

LLC2

line locked 1/2 clock output (13.5 MHz nominal) for backward

compatibility; do not use for new applications

XTALI

input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or

connection of external oscillator with TTL compatible square wave

clock signal

XTALO

24.576 MHz (32.11 MHz) crystal oscillator output; not connected

if pin XTALI is driven by an external single-ended oscillator

XTOUT

crystal oscillator output signal, auxiliary signal

Boundary scan test

TCK

I/pu

test clock for boundary scan test (with internal pull-up)[7]

TDI

I/pu

test data input for boundary scan test (with internal pull-up)[7]

TDO

test data output for boundary scan test[7]

TMS

I/pu

test mode select for boundary scan test or scan test (with internal

pull-up)[8]

TRST_N

I/pu

test reset for boundary scan test (active LOW with internal

pull-up); for board design without boundary scan connect

TRST_N to ‘ground’, e.g. through VSSD(CORE) or VSSD(IO)[8]

Test interface

TEST9

L11

I/pd