CS5378 datasheet(11/88 Pages) CIRRUS

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CS5378

DS639F2

SPI Registers

Digital Filter Registers

Name

Addr.

Type

# Bits

Description

SPICTRL

00 - 02

R/W

8, 8, 8

SPI Control

SPICMD

03 - 05

R/W

8, 8, 8

SPI Command

SPIDAT1

06 - 08

R/W

8, 8, 8

SPI Data 1

SPIDAT2

09 - 0B

R/W

8, 8, 8

SPI Data 2

Name

Addr.

Type

# Bits

Description

CONFIG

R/W

Hardware Configuration

RESERVED

01-0D

R/W

Reserved

GPCFG

R/W

GPIO[7:0] Direction, Pull-up Enable, and Data

RESERVED

0F-1F

R/W

Reserved

FILTCFG

R/W

Digital Filter Configuration

GAIN

R/W

Gain Correction

RESERVED

22-24

R/W

Reserved

OFFSET

R/W

Offset Correction

RESERVED

26-28

R/W

Reserved

TIMEBRK

R/W

Time Break Delay

TBSCFG

R/W

Test Bit Stream Configuration

TBSGAIN

R/W

Test Bit Stream Gain

SYSTEM1

R/W

User Defined System Register 1

SYSTEM2

R/W

User Defined System Register 2

VERSION

R/W

Hardware Version ID

SELFTEST

R/W

Self-Test Result Code

Table 3. SPI and Digital Filter Registers

Table 4. PLL and BOOT Mode Reset Configurations

PLL[2:0]

Mode Selection on Reset

111

32.768 MHz clock input (PLL bypass).

110

1.024 MHz clock input.

101

2.048 MHz clock input.

100

4.096 MHz clock input.

011

32.768 MHz clock input (PLL bypass).

010

1.024 MHz Manchester input.

001

2.048 MHz Manchester input.

000

4.096 MHz Manchester input.

Configuration Note:

States of the PLL[2:0] and BOOT pins are

latched immediately after reset to select modes.

These pins have a weak (~100 k

Ω) pull-up re-

sistor enabled by default. An external 10 k

Ω

pull-down is required to set a low condition.

BOOT

Mode Selection on Reset

EEPROM boot

Microcontroller boot

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