CS5378 datasheet(36/88 Pages) CIRRUS

36 / 88 page

CS5378

DS639F2

10. MODULATOR INTERFACE

The CS5378 performs digital filtering for a

∆Σ type

modulator. Signals from the

∆Σ modulators are

connected through the modulator data interface

(MDI).

10.1 Pin Descriptions

MCLK - Pin 11

Modulator clock output. Nominally 2.048 MHz or

1.024 MHz.

MSYNC - Pin 12

Modulator synchronization signal output. Generat-

ed from the SYNC input.

MDATA - Pin 13

Modulator data input, nominally 512 kbit/s.

MFLAG - Pin 14

Modulator flag input. Driven high when the mod-

ulator is unstable due to an analog over-range con-

dition.

10.2 Modulator Clock Generation

The MCLK output is a low-jitter, low-skew modu-

lator clock generated from the 32.768 MHz master

clock.

MCLK typically operates at 2.048 MHz unless an-

alog low-power modes require a 1.024 MHz mod-

ulator clock.

The MCLK rate is selected and the MCLK output

is enabled by bits in the digital filter CONFIG reg-

ister (0x00). By default MCLK is disabled and

driven low.

10.3 Modulator Synchronization

The MSYNC output signal follows an input to the

SYNC pin. MSYNC phase aligns the modulator

sampling instant to guarantee synchronous analog

sampling across a measurement network.

MSYNC is enabled by a bit in the CONFIG register

(0x00). By default SYNC inputs do not cause an

MSYNC output.

Figure 20. Modulator Data Interface

FIR

IIR

Filters

Filter

Output to High Speed Serial Interface

DC Offset

Correction

Output Rate 4000 SPS ~ 1 SPS

& Gain

MDATA

MFLAG

MDI Input

512 kHz

MCLK /

Generate

MSYNC

CLK

SYNC

MSYNC

SINC

Filter

MCLK

CS5378 数据表(PDF) 36 Page - Cirrus Logic

CS5378 数据表(HTML) 36 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载