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2601C–MICRO–06/08

AT89LS52

7.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset

(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user

must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When

the WDT is enabled, it will increment every machine cycle while the oscillator is running. The

WDT timeout period is dependent on the external clock frequency. There is no way to disable

the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-

flows, it will drive an output RESET HIGH pulse at the RST pin.

7.1

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH

and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches

16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every

machine cycle while the oscillator is running. This means the user must reset the WDT at least

every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to

WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When

WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-

tion is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be

serviced in those sections of code that will periodically be executed within the time required to

prevent a WDT reset.

7.2

WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-

down mode, the user does not need to service the WDT. There are two methods of exiting

Power-down mode: by a hardware reset or via a level-activated external interrupt which is

enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,

servicing the WDT should occur as it normally does whenever the AT89LS52 is reset. Exiting

Power-down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent

the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until

the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for

the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to

reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether

the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)

as the default state. To prevent the WDT from resetting the AT89LS52 while in IDLE mode, the

user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter

IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count

upon exit from IDLE.