22

2601C–MICRO–06/08

AT89LS52

Data Polling: The AT89LS52 features Data Polling to indicate the end of a byte write cycle. Dur-

ing a write cycle, an attempted read of the last byte written will result in the complement of the

written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs,

and the next cycle may begin. Data Polling may begin any time after a write cycle has been

initiated.

Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output

signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is

pulled high again when programming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code

data can be read back via the address and data lines for verification. The status of the individ-

ual lock bits can be verified directly by reading them back.

Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-

mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to

a logic low. The values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 62H indicates 89LS52

(200H) = 06H

Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the

proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -

500 ns.

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase

instruction. In this mode, chip erase is self-timed and takes about 500 ms.

During chip erase, a serial read from any address location will return 00H at the data output.

19. Programming the Flash – Serial Mode

The Code memory array can be programmed using the serial ISP interface while RST is pulled

to V

set high, the Programming Enable instruction needs to be executed first before other operations

can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is

required.

The Chip Erase operation turns the content of every memory location in the Code array into

FFH.

Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than

1/16 of the crystal frequency. With a 16 MHz oscillator clock, the maximum SCK frequency is 1

MHz.