10

 2007 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1189

Component Selection (Cont.)

sider conduction losses to determine FET suitability.

For a 5V in; 2.8V out at 14.2A requirement, typical FET

losses would be:

Using 1.5X Room temp R

e

p

y

t

T

E

FR

)

n

o

(

S

D

m

(

Ω)P

D

)

W

(e

g

a

k

c

a

P

5

2

0

4

3

L

R

I5

19

6

.

k

a

P

3

0

2

2

L

R

I5

.

0

19

1

.

k

a

P

0

1

4

4

i

S0

26

2

.

28

-

0

S

BO

BO

BO

BO

BOTT

TT

TT

TT

TTOM FET

OM FET

OM FET

OM FET

OM FET - Bottom FET losses are almost entirely due

to conduction. The body diode is forced into conduction at

the beginning and end of the bottom switch conduction

period, so when the FET turns on and off, there is very

little voltage across it, resulting in low switching losses.

Conduction losses for the FET can be determined by:

)

1

(

R

I

P

)

on

(

DS

2

O

COND

δ

−

⋅

⋅

=

For the example above:

e

p

y

t

T

E

FR

)

n

o

(

S

D

m

(

Ω)P

D

)

W

(e

g

a

k

c

a

P

5

2

0

4

3

L

R

I5

13

3

.

k

a

P

3

0

2

2

L

R

I5

.

0

13

9

.

k

a

P

0

1

4

4

i

S0

27

7

.

18

-

0

S

Each of the package types has a characteristic thermal

impedance. For the surface mount packages on double

sided FR4, 2 oz printed circuit board material, thermal

SO-8 are readily achievable. The corresponding tempera-

ture rise is detailed below:

(

e

s

i

R

e

r

u

t

a

r

e

p

m

e

T

O

)

C

e

p

y

t

T

E

FT

E

F

p

o

TT

E

F

m

o

t

t

o

B

5

2

0

4

3

L

R

I6

.

7

62

.

3

5

3

0

2

2

L

R

I6

.

7

42

.

7

3

0

1

4

4

i

S8

.

0

8

16

.

1

4

1

It is apparent that single SO-8 Si4410 are not adequate

for this application, but by using parallel pairs in each

position, power dissipation will be approximately halved

and temperature rise reduced by a factor of 4.

INPUT CAP

INPUT CAP

INPUT CAP

INPUT CAP

INPUT CAPAAAAACIT

CIT

CIT

CIT

CITORS

ORS

ORS

ORS

ORS - since the RMS ripple current in the

input capacitors may be as high as 50% of the output

current, suitable capacitors must be chosen accordingly.

Also, during fast load transients, there may be restrictions

on input di/dt. These restrictions require useable energy

storage within the converter circuitry, either as extra

output capacitance or, more usually, additional input ca-

pacitors. Choosing low ESR input capacitors will help maxi-

mize ripple rating for a given size.

G

G

G

G

GAAAAATE RESIS

TE RESIS

TE RESIS

TE RESIS

TE RESISTTTTTOR SELECTION

OR SELECTION

OR SELECTION

OR SELECTION

OR SELECTION - The gate resistors for the

top and bottom switching FETs limit the peak gate current

and hence control the transition time. It is important to

control the off time transition of the top FET, it should be

fast to limit switching losses, but not so fast as to cause

excessive phase node oscillation below ground as this can

lead to current injection in the IC substrate and erratic

behaviour or latchup. The actual value should be deter-

mined in the application, with the final layout and FETs.

CURRENT SENSE, LIMIT

CURRENT SENSE, LIMIT

CURRENT SENSE, LIMIT

CURRENT SENSE, LIMIT

CURRENT SENSE, LIMIT, DR

, DR

, DR

, DR

, DROOP AND OFFSET

OOP AND OFFSET

OOP AND OFFSET

OOP AND OFFSET

OOP AND OFFSET

The converter is protected and it’s loadline shaped by the

signals generated from the sense resistor and associated

components.

INDUCTOR

Ra

Rb

Rload

Rc

+

VOSENSE

Io

Vo

V

CS

DROOP

AND

OFFSET

CIRCUIT

CURRENT LIMIT CIRCUIT

Current Limit, Droop and Offset circuit

Current Limit is given by

I

At no load the output voltage is given by:

V

so the offset is:

V

and the droop is calculated as:

V

where R

For a full design procedure for droop and offset, see Appli-

cation Note AN97-9, “Using Droop and Vout Offset for im-

proved transient response”.