11

 2007 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1189

FOLDBACK CURRENT LIMITING

The SC1189 implements a “Hard Current Limit”

overcurrent protection for the switching supply output. In

a short circuit condition, this will lead to higher than nor-

mal power dissipation in the bottom side FETs. If this is

problematic, foldback current limiting can be easily and

inexpensively implemented to drastically reduce dissipa-

tion during output short circuit

Output Current Path

D1

1N4148

To CS+

To CS-

L1

Foldback current limit components

0

1

01

Breakpoint

Foldback current limit characteristics

For a complete design procedure for foldback current lim-

iting see Application Note AN01-2, “Foldback Current

Limit”. An abbreviated procedure is given below.

1) Choose values for I

S

O

CS

F

D

F

R

I

V

R

R

R

=

+

If this ratio > 1, the value of R

Then let R

2) Choose a short circuit current (I

not be too agressive with M, a value between 2 and 3

should be sufficient. Choosing too low a value for I

result in a high value for M and may cause startup prob-

lems due to insufficient current.

OS

OLIM

I

I

M

=

3) Choose V

)

R

R

(

V

)

1

M

(

R

R

V

M

R

F

D

CS

F

D

B

B

+

−

⋅

⋅

⋅

=

4) Calculate the ratio of the input divider

0.6V)

(

diode

of

drop

Voltage

Forward

V

where

V

V

V

V

)

R

R

(

R

F

IN

F

CS

B

C

A

C

≈

=

+

+

=

+

Choose R

SHOR

SHOR

SHOR

SHOR

SHORT CIR

T CIR

T CIR

T CIR

T CIRCUIT PR

CUIT PR

CUIT PR

CUIT PR

CUIT PRO

O

O

O

OTECTION - LINEARS

TECTION - LINEARS

TECTION - LINEARS

TECTION - LINEARS

TECTION - LINEARS

The Short circuit feature on the linear controllers is imple-

mented by using the Rds(on) of the FETs. As output cur-

rent increases, the regulation loop maintains the output

voltage by turning the FET on more and more. Eventually,

as the Rds(on) limit is reached, the FET will be unably to

turn on more fully, and output voltage will start to fall.

When the output voltage falls to approximately 50% of

nominal, the LDO controller is latched off, setting output

voltage to 0. Power must be cycled to reset the latch.

To prevent false latching due to capacitor inrush currents

or low supply rails, the current limit latch is initially dis-

abled. It is enabled at a preset time (nominally 2mS) after

both the LDOV and LDOEN rails rise above their lockout

points.

To be most effective, the linear FET Rds(on) should not be

selected artificially low, the FET should be chosen so that,

at maximum required current, it is almost fully turned on.

If, for example, a linear supply of 1.5V at 4A is required

from a 3.3V ± 5% rail, max allowable Rds(on) would be.

Rds(on)max = (0.95*3.3-1.5)/4 » 400m

Ω

To allow for temperature effects 200m

Ω would be a suit-

able room temperature maximum, allowing a peak short

circuit current of approximately 15A for a short time be-

fore shutdown.