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CMS3216LAH 数据表(PDF) 3 Page - FIDELIX |
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CMS3216LAH 数据表(HTML) 3 Page - FIDELIX |
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3 / 46 page ![]() Rev0.2, Aug. 2006 CMS3216LAx-75Ex Features - Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8, or full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 1.8V - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Special (-10℃ to +60℃) - Commercial (0℃ to +70℃) - Extended (-25℃ to +85℃) - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 54ball FBGA with 0.8mm ball pitch - CMS3216LAF : Normal - CMS3216LAG : Pb-Free - CMS3216LAH : Pb-Free & Halogen Free Functional Description The CMS3216LAx-xxxx family is high-performance CMOS Dynamic RAMs (DRAM) organized as 2M x 16. These devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.This is ideal for providing More Battery Life in portable applications such as wireless handsets. The device is compatible with the JEDEC standard LP-SDRAM specifications. Selection Guide 20ns 20ns 8ns 100MHz 20ns 20ns 7ns 133MHz 1.70-VDD 1.70-1.95V CMS3216LAx-75Ex t RCD CL=2 Access Time(t AC) CL=3 V DDQ V DD t RP Frequency Voltage Device Column Decoder Bank 0 Row Addr Latch/ Decoder Bank 1 Bank 0 Row Addr Latch/ Decoder Bank 0 Memory Array 2Kx8K Sense Amp Row Add Mux Write Drivers DQM Mask READ DATA LATCH Data Output Reg Column Address Latch Bank Control Logic Refresh Counter Addr Reg Data Input Reg DQM0- DQM1 DQ0 - DQ15 Column Decoder Enhanced Mode Reg Mode Reg Control Logic CKE CLK /CS /WE /CAS /RAS A0-A10 BS Logic Block Diagram |
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