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ATSAM2533 数据表(PDF) 13 Page - ATMEL Corporation |
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ATSAM2533 数据表(HTML) 13 Page - ATMEL Corporation |
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13 / 19 page ![]() 13 6396A–DRMSD–15-Oct-08 ATSAM2533 9.3 External ROM/Flash Timings Figure 9-3. RO/Flash Read Cycle WCS/ WA0- WA23 WOE/ WD0- WD15 tCSOE tRC tPOE tOE tDF tACE Table 9-3. External ROM/Flash Timing Parameters Symbol Parameter Min Typ Mx Unit tRC Read cycle time 5*tck - 6*tck ns tCSOE Chip select low/address valid to WOE low 2*tck-5 - 3*tck+5 ns tPOE Output enable pulse width - 3*tck - ns tACE Chip select/address access time 5*tck-5 - - ns tOE Output enable access time 3*tck-5 - - ns tDF Chip select or WOE high to input data Hi-Z 0 - 2*tck-5 ns |
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