2

6396A–DRMSD–15-Oct-08

ATSAM2533

UART, and the CODEC control interface, with minimum intervention from the control processor.

2.

ATSAM2533 IC Architecture Block Diagram

Figure 2-1.

ATSAM2533 IC Architecture Block Diagram

P16 Processor

16-bit CISC

Processor Core

includes

256 x 16 Data RAM

32K x 16 RAM

ROM

Debug/Flash Prog

MMU

Memory

Management

Unit

I/O Functions

Includes

Control/Status

MIDI USART

Timers

CODEC Data I/F

Host I/F FIFO

Synthesis/DSP

64 Slots

RISC DSP Core

Includes:

512 x 32 Alg RAM

128 x 28 MA1 RAM

256 x 28 MA2 RAM

256 x 28 MB RAM

256 x 16 MX RAM

256 x 12 MY RAM

64 x 13 ML RAM

ATSAM2533

CODEC

+ DAC

ROM

or

Flash

MIDI

8-bit Port

Debug

Flash Prog